In a process technique of a semiconductor integrated circuit, with the advancement in microfabrication, a mask technique has become significant, in addition to an exposure technique, in order to form a pattern with a width not more than a wavelength of light. When a Numerical Aperture (NA) is increased for forming a micropattern, a Depth Of Field (DOF) is reduced, so that the affect of a base is non-negligible when forming a pattern. For example, the variation in the width of a gate electrode, which is caused by a step of the base, significantly appears in an operation speed of a transistor or leak current, which affects the transistor performance. Therefore, a pattern that is to be actually formed is generally simulated and evaluated with the use of a mask pattern, in order to form a desired width of a gate electrode.
As semiconductor devices have been using finer patterns due to higher integration these days, the influence of an optical proximity effect appears greatly in an exposure process, making it difficult to manufacture semiconductor devices according to the design data. To prevent this from occurring, Optical Proximity Correction (OPC) technique for correcting a circuit pattern in design data has been generally employed by obtaining the influence of the optical proximity effect in order to obtain dimensions as designed.
When acquiring data for OPC, a substrate having no step of a Shallow Trench Isolation (STI) is generally employed. The substrate has no active region or no device isolation. An oxide film, polysilicon film and insulating film based hard mask material are laminated on a flat substrate, a reflection preventing film and a resist are applied thereon, and the resultant is transferred and etched with a mask having a test pattern according to various sizes such as line/space. Then, the size data after the processing is measured. A model equation is derived over the basis of this measured data and the optical simulation so as to perform a correction of a mask pattern. Specifically, the same correction is executed, regardless of a type of a transistor, and further, the difference in the size of an active region is not considered.
As represented by a transistor having different power supply voltage, a difference is produced in a retreat amount of the oxide film, for example High Density Plasma (HDP) oxide film, embedded into the STI region due to the difference in the type of ion of implanted impurity, the dosage, or the number of times of wet process. The same problem arises in the process of forming multi-gate oxide transistors. Further, the step varies depending upon the size of the active region even in transistors of the same type. As a result, there is a difference between an actual product and the result of the simulation.
Specifically, suppose the case in which an active region is formed so as to project from an STI region. The STI region has a buried insulating film 102 as shown in FIG. 1B. When the gate width (W width) or source-drain width (SD width) of the active region 110 on a silicon substrate 101 is different, as shown in FIG. 1B, in the active region 110 divided by the W width and the SD width over a source (S) region and a drain (D) region shown in FIG. 1A, the thickness of a gate oxide film 103 or a sacrificial oxide film that is to be formed varies. The reason for this is because, when the oxide film is formed, the oxidation rate in the direction of the side wall is faster, and hence, the thicker oxide film is formed in the active region with the narrow W width, compared to the active region with the wide W width, for example.
As shown in FIG. 2, the following wet process, for example hydrofluoric acid treatment process, makes a sinking amount of the active region 110 different due to the difference in the W width or the SD width of the active region 110, so that the variation of the step increases. As shown in FIGS. 3A and 3B, this step affects the application state of a reflection preventing film 105 on a gate electrode film 104 in the next gate forming process, with the result that the thickness of the reflection preventing film 105 or, depending on the situation, the thickness of the resist 106 becomes non-uniform. As a result, the DOF or reflectivity varies, whereby the non-uniform size depending upon the width of the active region is produced in the patterning for forming the gate electrode 108.
A trimming technique has recently been used in an etching in order to process a gate electrode having a smaller size than the size of the patterning. The difference in the thickness of the reflection preventing film 105 affects an etching shift amount by the trimming of the reflection preventing film 105. When the thickness of the reflection preventing film 105 differs according to the step, the etching shift of the gate electrode 108 in the processing is very likely to differ at various parts.
It is difficult, from the viewpoint of a process flow, to improve the step between the device isolation region and the active region for every type of transistor. Therefore, the influence by this step becomes a significant subject.